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Altreonic successfully delivers on the EuroCPS NoFist project

PRESS RELEASE

Pressemitteilung • Communiqué de Presse • Comunicato Stampa

Altreonic successfully delivers on the EuroCPS NoFist project 

(Novel Fine Grain Space and Time Partitioning for a Mixed Criticality Platform)

In the project, supervised by Thales TRT, Altreonic ported and further developed VirtuosoNext Designer, providing as an industry’s first fine-grain space and time portioning. The latter enables non-stop hard real-time processing by recovering from runtime faults in microseconds on the selected Freescale T2080 platform.

Video course by Leslie Lamport on TLA+

Leslie Lamport, the man behind TLA+/TLC, the formal modeling language we used to develop our RTOS kernel has started a series of video lectures on TLA+. If interested in a comprehensive and pragmatic approach to formal modelling, we can only recommend it.

The webpage with a discussion forum is here with the videos here

Altreonic shows novel VirtuosoNext Designer at Hannover Messe

Altreonic has been demonstrating VirtuosoNext at the Hannover Messe, 24-28 April on the EUROCPS booth with Thales TRT. Visit us Hall 3, Booth E02 (European Comission). Altreonic's team has been meeting many interested visitors at the Hannover Messe April 24-28. Highlights were the novel City-KURT concept as well as VirtuosoNext.

 

VirtuosoNext™ Designer on Freescale QorIQ T2080/1

The fine grain memory protection in combination with microsecond real-time performance and a small code size is a breakthrough for VirtuosoNext Designer. In combination with the static programming model that eliminates many known safety and security risks, it delivers unprecedented real-time performance in combination with fine-grain partitioning for safety and security critical applications. 

Altreonic has now ported VirtuosoNext™ Designer to the Freescale QorIQ T2080/1 processor. The chip has 8 floating point cores implemented as 4 CPUs with a dual register set running at 1.8 GHz. The latest port of VirtuosoNext Designer delivers unprecedented hard real-time capability in the microsecond range in combination with fine grain task level space and time partitioning for embedded safety-critical applications. 

In contrast to traditional hypervisor based partitioning schemes, VirtuosoNext™ protects each application task separately in memory with a real-time response still available in the microseconds range as one expect from using an RTOS.  Moreover, the code size is measured in Kbytes, allowing optimal use of the on-chip caches for best performance.

From the archives: the origins of VirtuosoNext

VirtuosoNext Designer can be considered a 5th generation of the Virtuoso RTOS, whose origins go back to 1991. It was the first RTOS that was completely distributed and mainly used for parallel DSP applications, often in the demanding aero-space-defense domain. Some target systems had 12000 processors, the most prominent one was ESA's Rosetta spacecraft.

Altreonic invited speaker at HIPEAC, Spring CSW in Porto

Eric Verhulst will be speaking at the Spring Computer Systems Week in Porto, presenting at a thematic session on Program transformation and analysis approaches for future computing systems (ProTrans). Title of the presentation: "From CSP to Interacting Entities for programming and modelling". Details can be found here.

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