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OpenComRTOS support for Synopsis' ARC processor cores

Altreonic has now developed a first port of its OpenComRTOS Designer™ to the ARC family of processor cores of Synopsis, extending further the range of supported processors. This work was done in the context of the Artemis CRAFTERS project that focuses on the design and programming challenge of developing applications with many- and multicore architectures. 

OpenComRTOS Designer new v.1.6 release

Altreonic has recently added new features to its network-centric RTOS that make programming systems with multiple, even heterogeneous processors even easier than before. The new support extend the virtual shared memory and virtual single processor support.

Supports system-wide shared data structures: virtual shared memory model
OpenComRTOS is the unique formally developed RTOS that can program seamlessly even heterogenous systems from a single processor to 1000's of processing nodes. It comes with a visual modeling environment whereby the developer independently specifies his parallel multi-processor target system and application architecture. Tasks and interaction entities can then be transparently mapped to any node in the system, even when the processors are of a different type. With prioritised scheduling and support for distributed priority inheritance, the system remains real time predictable with a typical code size of less than 10 KB per processing node. From v.1.6 of the OpenComRTOS Designer environment on, the developers benefits from a streamlined kernel source code and new features. OpenComRTOS Designer is however a lot more than an RTOS. Read further ....

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Altreonic HIRES2013 Workshop

Altreonic presents a working paper entitled: 

"A Formalised Real-time Concurrent Programming Model for Scalable Parallel Programming",authors Eric Verhulst, Bernhard H.C. Sputh at the Workshop on High-performance and Real-time Embedded Systems(HiRES 2013) January 23, 2013, Berlin, Germany. 

Held in conjunction with the 8th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC 2013)



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